MIT Department of Electrical Engineering & Computer Science
Thread-Level Data Speculation: Facilitating Automatic Parallelization for Single-Chip Multiprocessors
Todd C. Mowry
University of Toronto
Thursday, May 8, 1997
2:00 PM (1:45 refreshments)
Room NE43-518
EECS Special Seminar
Abstract
As we look to the future, and the prospect of a billion transistors on a chip,
it seems inevitable that microprocessors will exploit having multiple parallel
threads. To achieve the full potential of these "single-chip multiprocessors,"
however, we must find a way to parallelize non-numeric applications.
Unfortunately, compilers have had little success in parallelizing non-numeric
codes due to their complex access patterns. In this talk, we explore the
potential for using "thread-level data speculation" (TLDS) to overcome this
limitation by allowing the compiler to view parallelization solely as a
cost/benefit tradeoff, rather than something which is likely to violate program
correctness. Our experimental results demonstrate that with realistic compiler
support, TLDS can offer significant program speedups. We also demonstrate that
through modest hardware extensions, a generic single-chip multiprocessor could
support TLDS by augmenting its cache coherence scheme to detect dependence
violations, and by using the primary data caches to buffer speculative state.
Hosts: Professor B. Liskov and Professor F. Kaashoek
URL of this page:
http://www-eecs.mit.edu/AY96-97/events/51.html
Created: Apr 30, 1997
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Modified: Jun 24, 1997
This announcement is from the MIT EECS 1996-97 archive.
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